Application Note: Shunt Resistor PCB Layout

1. Why Layout Matters

A current sense resistor may have been specified carefully for TCR, tolerance, and power rating — but a poor PCB layout can introduce errors that dwarf those of the component itself. Two mechanisms dominate:

• Trace resistance: PCB copper traces have non-negligible resistance. At 35 µm (1 oz) copper, a 1 mm wide, 10 mm long trace has approximately 5 mΩ of resistance. For a 5 mΩ sense resistor, this is a 100% error if the sense voltage taps in at the wrong point.
• Parasitic inductance: High-frequency currents (switching power supplies, PWM motor drives) induce voltages across trace inductance (V = L × dI/dt). A poorly laid out sense path can show large transient artefacts unrelated to the resistor value.

2. Standard 2-Terminal Layout

For sense resistances above approximately 20 mΩ, a standard 2-terminal connection is usually adequate, provided the layout rules below are followed.

3. 4-Terminal Kelvin Layout

Below 10–20 mΩ, even small trace resistances become significant. The Kelvin connection (also called a 4-wire or force-sense connection) eliminates the contribution of connection resistance from the measurement.

Two approaches are available:

• Component-level Kelvin: Use a 4-terminal resistor such as the CSSK, which has separate outer force terminals and inner sense terminals. The component construction itself enforces the correct sense-tap position.
• Layout-level Kelvin: Use a standard 2-terminal resistor with a split-pad layout. Each end of the resistor has two distinct pads — one for the current path and one for the sense tap.

Kelvin Layout Rules

1. The sense pad must be connected as close to the resistor termination as physically possible — ideally directly adjacent to the force pad, not downstream of it.
2. The sense trace should not carry any current. Route it with minimum width (0.1–0.15 mm is sufficient) directly to the differential input of the current-sense amplifier or ADC.
3. Match the lengths and routing of the two sense traces to minimise differential offset from trace inductance. A difference in length of 1 mm at a 100 MHz switching harmonic introduces approximately 0.5 nH of differential inductance imbalance.
4. Do not share vias between the force path and the sense path. A shared via carrying the full load current introduces resistive voltage drop that corrupts the sense measurement.
5. If using a 4-terminal component such as the CSSK, respect the manufacturer's recommended land pattern — do not merge the inner and outer pads.

4. Minimising Parasitic Inductance

In switching power supplies, inverters, and motor controllers, current slew rates of 1–10 A/µs are common. At these rates, a parasitic inductance of just 1 nH generates a voltage of 1–10 mV — comparable to the sense voltage across a 1 mΩ resistor at 1 A.

Sources of Parasitic Inductance

• Current loop area: The inductance of a current loop is approximately proportional to the area enclosed by the loop. Keep the high-current trace loop as small as possible.
• Component inductance: Wirewound and some thick film resistors have significant self-inductance. For switching applications, specify non-inductive wirewound or use metal alloy/foil construction. See the CSNL series for a specifically low-inductance metal alloy option.
• Via inductance: Each via contributes approximately 0.5–1 nH. Minimise the number of vias in the current path.

Low-Inductance Layout Techniques

• Route the return current path (ground or negative bus) directly adjacent to the forward current path on the same or adjacent layer, so the electromagnetic fields partially cancel.
• Use flood fill (copper pours) for the current path on inner layers to reduce trace inductance.
• Place bypass capacitors close to the current sense amplifier inputs to filter switching transients on the sense lines.
• Consider adding a small RC filter (e.g. 10 Ω + 100 pF) differentially at the sense amplifier input to attenuate high-frequency noise without significantly affecting the DC/low-frequency measurement.

5. Thermal Management

Self-heating in the sense resistor shifts its resistance via TCR, introducing a systematic measurement error that increases with load current. Good thermal design minimises this effect.

Estimating Self-Heating

The temperature rise above ambient is:

ΔT = P × θJA

Where θ_JA is the thermal resistance from junction to ambient (typically 50–150 °C/W for chip resistors, depending on PCB copper area). The resulting resistance error is:

ΔR/R = TCR × ΔT × 10⁻⁶

Reducing Thermal Resistance

• Increase the copper pad area. Extending the pads by 2× can reduce θ_JA by 30–50%.
• Add thermal vias beneath the resistor pads to transfer heat to inner copper layers or the board underside.
• Use a thick copper PCB (2 oz or 3 oz) for high-current sense applications.
• For very high power (the HCS series up to 10 W), consider a metal-core PCB or chassis mounting.

6. Layout Checklist

• ☐ Sense voltage taps connect at the resistor pads, not the trace
• ☐ Sense traces routed as a matched-length differential pair
• ☐ No shared vias between force and sense paths
• ☐ Sense traces do not run parallel to high-current conductors for more than a few mm
• ☐ Current loop area minimised
• ☐ Bypass/filter capacitor placed at sense amplifier input
• ☐ Copper area on pads sized for thermal dissipation
• ☐ Thermal vias included if power dissipation > 0.5 W
• ☐ Non-inductive resistor construction selected for switching applications
• ☐ If R < 10 mΩ: Kelvin layout or 4-terminal component used